Using ...: Digital System Test And Testable Design:

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in Digital System Test and Testable Design: Using ...

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage

Memory fault models, MBIST (Memory BIST) methods, and functional procedures. The book by Zainalabedin Navabi (2010) is a

Gate-level faults, fault collapsing, and structural modeling in Verilog.

Scan architectures, RT-level scan design, and Boundary Scan (JTAG). More information can be found at Springer Nature

It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.